E cient Use of Large Don't Cares in High-Level and Logic Synthesis
نویسندگان
چکیده
This paper describes optimization techniques using don't-care conditions that span the domain of highlevel and logic synthesis. The following three issues are discussed: 1) how to describe and extract don't-care conditions from high-level descriptions; 2) how to pass don't-care conditions from high-level to logic synthesis; and 3) how to optimize the logic using don't-care conditions. E cient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very e ective for both area and delay minimization.
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